eprintid: 173
rev_number: 4
eprint_status: archive
userid: 6
dir: disk0/00/00/01/73
datestamp: 2008-10-13
lastmod: 2015-05-29 19:48:41
status_changed: 2009-04-08 16:55:18
type: report
metadata_visibility: show
item_issues_count: 0
creators_name: Piché, Robert
creators_name: Keyes, Edward
contributors_name: Baumann, Michael
contributors_name: Bose, Chris
contributors_name: Dame, Lorraine
contributors_name: Dechene, Isabelle
contributors_name: Goncalves, Maria Inez
contributors_name: Israel, Robert
contributors_name: Lutscher, Frithjof
contributors_name: Lyder, David
contributors_name: Macdonald, Colin
contributors_name: McNulty, Jenny
contributors_name: Morris, Joy
contributors_name: Neudauer, Nancy Ann
contributors_name: Ong, Benjamin
contributors_name: Aruna, Šalkauskas
contributors_name: Seyffarth, Karen
contributors_name: Stevens, Brett
contributors_name: Vassilev, Tzvetalin
contributors_name: Wetton, Brian
contributors_name: Youbissi, Fabien
title: Stitching IC Images
ispublished: pub
subjects: other
subjects: telecom
studygroups: ipsw6
companyname: Semiconductor Insights
full_text_status: public
abstract: Image stitching software is used in many areas such as photogrammetry, biomedical imaging, and even amateur digital photography. However, these algorithms require relatively large image overlap, and for this reason they cannot be used to stitch the integrated circuit (IC) images, whose overlap is typically less than 60 pixels for a 4096 by 4096 pixel image.

In this paper, we begin by using algorithmic graph theory to study optimal patterns for adding IC images one at a time to a grid. In the remaining sections we study ways of stitching all the images simultaneously using different optimisation approaches: least squares methods, simulated annealing, and nonlinear programming.
problem_statement: Errors in stitching (or mosaicing) of integrated circuit (IC) images cause errors in the automated generation of the schematic. This increases costs and introduces delays as engineers must step in with interactive computer tools to correct the stitching. Our goal was to develop automated image stitching methods that keep stitching errors under F/2, where the minimum feature size F is around 10 pixels.
date: 2002
date_type: published
pages: 25
citation:   Piché, Robert and Keyes, Edward  (2002) Stitching IC Images.  [Study Group Report]     
document_url: http://miis.maths.ox.ac.uk/miis/173/1/semiconductor.pdf