eprintid: 590
rev_number: 11
eprint_status: archive
userid: 10
dir: disk0/00/00/05/90
datestamp: 2012-10-29 16:31:01
lastmod: 2015-05-29 20:12:46
status_changed: 2012-10-29 16:31:01
type: report
metadata_visibility: show
item_issues_count: 0
creators_name: van den Akker, M
creators_name: Beelen, T
creators_name: Bisseling, R
title: Routing for analog chip designs at NXP Semiconductors
ispublished: pub
subjects: discrete
subjects: telecom
studygroups: esgi79
companyname: NXP
full_text_status: public
abstract: During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP.
This resulted in an heuristic approach, which we presented at the end of the
week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.
date: 2011
citation:   van den Akker, M and Beelen, T and Bisseling, R  (2011) Routing for analog chip designs at NXP Semiconductors.  [Study Group Report]     
document_url: http://miis.maths.ox.ac.uk/miis/590/1/Amst115.pdf